A nonvolatile memory using ferroelectric materials, which can reverse its polarization according to the voltage polarities applied thereto, has, in principle, the same writing and reading times. Further, at a quiescent or non-operative state (backup time) the afore-mentioned nonvolatile memory keeps polarization (residual polarization), even if no voltage is applied thereto. Therefore, it has been regarded as an ideal nonvolatile memory.
Conventionally, various semiconductor nonvolatile memories have been proposed using ferroelectric capacitors. Disclosed in U.S. Pat. No. 4,149,302 is a construction where ferroelectric capacitors are integrated on a silicon (Si) substrate. Disclosed in U.S. Pat. No. 3,832,700 is a construction having ferroelectric films disposed on the gate electrode of a MIS-type transistor.
A nonvolatile memory cell generally comprises, as shown in FIG. 8, an N-type transistor TR which has a gate electrode G connected to a word line W, a drain electrode D connected to a bit line B and a source electrode S connected to one electrode of a ferroelectric capacitor C. The other electrode of the ferroelectric capacitor C is connected to a plate line P. A recently proposed practical semiconductor construction of such a memory cell is shown in FIG. 9. The semiconductor construction shown in FIG. 9 comprises an N-type MOS transistor TR which has a polysilicon (polycrystal silicon) gate electrode 3 formed through a gate oxide film 2 on a P-type silicon substrate 1. Source and drain zones 4 and 5 are N-type high concentration diffusion regions formed in the silicon substrate 1 by using a self-aligning diffusion technique. A ferroelectric capacitor C is formed on an interlayer insulation film 7, such as phosphoric glass, etc., disposed between layers on a local oxide film (LOCOS) 6 for isolating elements. The ferroelectric capacitor C on the interlayer insulation film 7 is composed of a lower electrode 8 made of platinum (Pt), etc., a ferroelectric film 9 such as PZT, etc. and an upper electrode 10 of gold (Au) or platinum (Pt), stacked in that order. The source zone 4 which is a high concentration diffusion region and the upper electrode 10 are connected to each other with a wiring 12 made of Al through a contact hole 11. The reference number 13 indicates a second interlayer insulation film made of phosphoric glass and the like.
Gold (Au) and platinum (Pt), which form the upper electrode 10, are precious metals which do not react with the ferroelectric film and thus achieve a good interface property. Therefore, they are often used as the electrode of a ferroelectric capacitor. Also, because platinum (Pt) has a lattice constant near that of the ferroelectric material, such as PZT, the effect of improving the crystallization is expected, and as a result, platinum is used more frequently than gold.
The platinum (Pt) or gold (Au) of the upper electrode 10, however, readily reacts with the Al of the wiring electrode 12 at a temperature of around 300.degree. C. Consequently, on carrying out an annealing process and on forming a final protection film (a passivation film) after the formation of the wiring electrode 12, a reaction of the Al of the wiring electrode with the upper electrode 10 reaches the interface of the upper electrode 10 and the ferroelectric film 9, resulting in a decrease of the residual polarization, i.e. a deterioration of the electrical properties such as a decrease of a signal charge, a decrease of the relative dielectric constant Es, etc.
In addition, as shown in FIG. 9, in the construction of the ferroelectric capacitor C formed on the interlayer insulation film 7 on the local oxide film 6, the ferroelectric capacitor C is formed by effectively utilizing a space on the local oxide film 6. The length of the wiring electrode 12 between the source zone 4 and the upper electrode 10, however, is too prolix, which results in the increase of the memory cell areas.
A memory cell structure in which, as shown in FIG. 10, the ferroelectric film 9 is directly accumulated over the source zone 4 was manufactured. In this structure, an upper electrode 14 of platinum (Pt) is formed on the ferroelectric film 9, and is connected to a plate line P (not shown) through a wiring electrode 16 of Al. Under the ferroelectric film 9, through a contact hole in an interlayer insulation film 7 of a phosphoric doped glass and the like, the lower electrode 17, made of material such as Pt, is formed. In such a structure, after the wiring electrode 16 has been formed, an annealing treatment was carried out to improve the characteristics of the ferroelectric capacitor and a final protection film (a passivation film) was formed. However a reaction of the upper electrode 14 with the wiring electrode 16 occurred. Thus, normal operation of the memory could not be expected.
For the afore-mentioned reasons, in the structures shown in FIGS. 9 and 10 have the problem that the method of improving the characteristics of the ferroelectric substance is not compatible with the formation of the final protection film.
In view of the aforesaid problems of the conventional devices, the object of the present invention is to provide a semiconductor device having a structure in which the formation of the passivation film, the annealing treatment, etc. can be achieved without impeding the function of a nonvolatile memory having a ferroelectric substance therein.